A key goal in designing computer memory busses is to maximize their usable bandwidth. A short bus cycle time is required to achieve this, but that alone does not ensure that the usable bandwidth of the bus will be comparable to its electrical bandwidth because the bus must also have a high efficiency (conventionally defined as the ratio of the usable bus bandwidth to its electrical bandwidth) to achieve that goal.
Indeed, a short bus cycle time is of relatively little value for increasing the usable bandwidth of a conventional circuit switched bus because the circuit switching of the bus serializes the request/reply pairs for successive transactions on a transaction-by-transaction basis. As is known, a cache memory system can be employed for reducing the number and frequency of the main memory transactions a computer system is required to perform, but in high performance systems the traffic on the memory bus usually still is a dominant performance limiting factor.
Unfortunately, the access time of economically practical main memory typically is several times longer than the minimum realizable bus cycle time, so the usable bandwidth of a circuit switched bus tends to be limited by the main memory access time. In systems having cache memory, the wasted "wait" cycles of a circuit switched bus (i.e., its wasted bandwidth) may be reduced by increasing the size of the main memory/cache memory data transport unit, thereby amortizing the bus wait cycles over larger blocks of data. However, this approach tends to increase the bandwidth load that is placed on the bus by the processor or processors, which at least partially negates the benefit of the larger data transfer unit.
Others have recognized that the bandwidth penalty caused by idle bus cycles can be avoided by employing a "packet switched" bus (sometimes also referred to as a "split cycle" bus, or a "pending" bus). Packet switching of the bus dissociates the requests and the replies of bus transactions from each other, thereby permitting requests and replies for multiple transactions to be interleaved on the bus. As a general rule, idle bus cycles can be avoided simply by dissociating the requests and replies of the transactions in which main memory participates (i.e., the "main memory transactions"). However, it has been found that it is advantageous to dissociate the requests and replies of all bus transactions, so that a variable number of bus cycles (in excess of the implementionally dependent minimum number of cycles) may intervene between any request and its corresponding reply, subject only to the possible expiration or abortion of a request to which no reply is received within a predetermined timeout period. This essentially complete dissociation of all requests and replies helps eliminate bus deadlocks, while making it easier to interface the bus with non-synchronized devices, such as with the memory busses of dissimilar or "foreign" computer systems, including industrial standard systems. Furthermore, it facilitates the use of interleaved main memory modules, and simplifies the solution to the cache consistency problem for multiprocessors having multilevel, hierarchical cache memory systems.
Usable bus bandwidth and cache consistency are related but separable issues. As will be appreciated, cache consistency is a more detailed consideration because it is a specific requirement for busses which provide access to multiple cached copies of shared data while permitting different ones of the cached data copies to be updated under the control of different processors, such as in multiprocessors.
There are several known solutions to the cache consistency problem for circuit switched busses. See, for example, a copending and commonly assigned United States patent application of Pradeep S. Sindhu et al, which was filed Nov. 12, 1986 under Ser. No. 929,544 on "Multi-Level Cache Memory Trees for Multiprocessors" now abandoned. However, the known techniques for maintaining cache consistency are not directly applicable to packet switched busses See, Andrew W. Wilson, Jr., "Hierarchical Cache/Bus Architecture for Shared Memory Multiprocessors," Computer Architecture Conference (IEEE/ACM), 1987, pp 244-252.